Zen 2 architecture and the first seven nanometers for data centers
AMD introduced the Epyc Rome 64-core server processors based on the new 7nm Zen 2 architecture and the newly designed Chiplet Design multiple chip design.
These are the first x86 processors in the world, manufactured with 7 nm standards. Before that, in September 2018, Bionic's first mobile processors for this process were introduced by Apple. At the end of September, Huawei announced the release of the Kirin 980 mobile processor with 7 nm standards, but in both cases we are talking about ARM processors.
So the company was not only the first to announce the transfer of its server processors to the most accurate technical process to date but also managed to double the number of cores per chip. In the case of using a Rome chip in combination with motherboards for two processors, such a platform will provide 128 cores and 256 computational threads.
The previous generation of AMD processors had a record 32 processing cores per chip. Intel, in turn, promises to start producing the 48-channel Cascade Lake server chips next year. To date, Xeon server processor flags have 28 cores.
Already in 2019, AMD intends to transfer all its processor lines to the Zen 2 architecture with 7 nm standards. Now, according to the company, the deliveries of Rome's first generation Epyc processor samples based on this architecture to key customers have already begun.
64-core Epyc Rome processors with 7 nm standards
AMD also introduced the first Radeon Instinct MI60 and MI50 graphics accelerators world-wide, built according to 7 nm technology standards and designed to function as part of data center equipment. Like processors, they are manufactured in TSMC production facilities.
The new products have become the company's first accelerators, equipped with a new PCI Express 4.0 bus. The launch of the mass traditions of both models was promised before the end of 2018.
64 Core Epyc Rome: how it works
The double number of Epyc Rome processor cores was made possible by using a multi-chip array called Chiplet Design, where eight eight-computing core computing units and 16 computational flows are placed symmetrically on the sides of the I / O with controllers and interfaces.
Chiplet Design Multi-Chip Layout
For communications between the x86 computing unit and the interface unit, there is an Infinity Fabric high speed internal bus. Due to the fact that the I / O unit is produced by the 14 nm rules, its dimensions have proved to be disproportionately large compared to computer units, which were constructed according to the 7 nm rules.
Epyc Rome 64-core processor
In the development of the new Zen 2 architecture, AMD engineers do not restrict the redesign of the new processing technology. The new generation of processors of the company will receive an improved computer pipeline with a sophisticated branch prediction unit, additional security features.
The doubling unit for calculating floating points was 256-bit, the number of orders executed per clock, according to the company, increased by 52%. AMD expects the overall server performance in the link will double and mobile work performance will increase fourfold.
AMD promises to double the performance of servers in Epyc Rome
Each Epyc Rome processor supports eight DDR4 memory channels with a total capacity of up to 4GB per socket. New Epyc Rome processors based on 64-core servers will receive support for up to 128 PCIe 4.0 lines per slot so they are fully compatible with the new Radeon Instinct MI60 and MI50 graphics adapters.
In addition, Epyc Rome also backs full backward compatibility with the current Epyc Naples platform platforms and, in addition, with Milan's future AMD processors based on the Zen 3 microarchitecture.
New graphic Vega accelerators and future plans
The new Radeon Instinct MI60 and MI50 graphics accelerators, designed to handle complex tasks, including artificial intelligence, are based on the world's first graphics processors based on the improved 7-nm Vega architecture.
Graphic accelerator Radeon Instinct MI60
The Chip, Vega 20 navigation accelerator, according to the company, contains 13.28 billion Transistors measuring 331 square meters. mm The Vega 10 chip contains 12.5 billion transistors.
AMD Vega 20 GPU structure
The Radeon Instinct MI60 graphics processor with 4096 to 1800 MHz processors has 32 GB of HBM2 memory with a bandwidth of 1 TB / s, and the Radeon Instinct MI50 accelerometer with 3840 MHz processors up to 1746 MHz is equipped with 16 GB of analogue memory. The Thermopacket of both solutions, according to AMD, does not exceed 300 watts.
The industry's first PCIe 4.0 bus support
Instinct MI60 and MI50 accelerators support support for the PCIe 4.0 x16 interface, but there is support for two Infinity Fabric bus lines via an external PCIe bus. Thanks to data exchange between cards at speeds of up to 200 GB / s, it is possible to combine up to four cards into computing blocks.
For the MI60 accelerator, the performance is stated at 7.4 TFlops, with a 64-bit floating point calculation (FP64) and up to 14.7 Tflops in FP32 mode, for the MI50 accelerator with a capacity of up to 6.7 TFlops and 13.4 Tflops respectively.
AMD's closest plans
Speaking for the near future, AMD representatives announced plans to supply MI60 accelerators by the end of 2018. The company's next graphic decision, according to the commented plans, still has the functional name MI-Next but has not been announced technical details or release dates for the new product.